职位&公司对比

职位详情

• 北京
• 10年以上
• 本科

• 有数字后端工程师经验
• 5年以上数字后端工程师经验
• 16nm-7nm
• 低功耗设计经验
• 成功流片经验
• 量产经验
• 后端EDA工具
• 功耗分析
• IREM

Job Responsibilities: 1. Responsible for power analysis of chips from Netlist to GDS, including dynamic来自BOSS直聘 power consumption, static power consumption, IR voltage drop analysis, etc., to ensure that the design meets power consumption requirements; 2. Plan and design the power network, optimize power integrity, and ensure the reliability and efficiency of the power network; 3. Participate in the low-power design process and provide power optimization suggestions; 4. Conduct power consumption simulation, establish a power consumption model, and analyze the power consumption performance under different working modes; 5. Develop and optimize the power consumption analysbossis process to improve analysis efficiency and accuracy. Job requirements: 1. Master's degree holder with at least 5 years of experience and bachelor's degree holder with at least 7 years of experience in digital backend power consumption analysis. Candidates withboss successful chip fabrication experience are preferred; 2. Proficient in power analysis methods, proficient in using mainstream power analysis tools, familiar with the use and optimization of EDA tools; 3. Profic直聘ient in scripting languages such as Tcl, Perl, Shell, etc., able to write automated scripts to improve work efficiency; 4. Familiar with advanced process flow and understand the power consumption characteristics of different process nodes; 5. Possess rich experience in power network planning and design, able to optimize power integrity; 6. Familiar with low-power design methods and able to providekanzhun effective power optimization suggestions; 7. Able to conduct power consumption simulation and modeling, and analyze power consumption performance under different working modes.