职位&公司对比

职位详情

• 北京
• 3-5年
• 本科

• PCIe
• DDR
• P&R

Job Summary As a member of the core backend team, you will be responsible for the physical implementation (from netlist to tapeout) of a highly complex SOC utilizing state of the art process technology Description 1.Work with FE team to understand chip直聘 architecture and drive physical aspects early in design cycle. 2.Design automation; Construct, Guide, Modify, Enhance Timing tools and flows. 3.Top level floorpBOSS直聘lan, partition floorpan, P&R, timing and physical sign off. Key Qualification 1.The ideal candidate will have a minimum of 3 years of physical design experience, with recent successful tapeouts in deep sub-micron technology. 2.Expert in top /block level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification. 3.Experienced in industry standard tools, understand their capabilities and underlying algorithms. 4.Strong communication skbossills. 5.Familiar with sub-micro Synthesis, PR and power sign off tool is a plus.